1. Field of the Invention
This invention relates to a nonvolatile semiconductor memory device having memory cells stacked vertically and more particularly to a nonvolatile semiconductor memory device in which the structure for applying substrate potential is improved and a manufacturing method thereof.
2. Description of the Related Art
Conventionally, as one of electrically erasable programmable read-only memories (EEPROMs), a NAND flash memory that can be integrated with high integration density is widely used. In order to further increase the capacity of the NAND flash memory, it is required to further miniaturize the device or perform a multivalue storage operation. However, the degree of miniaturization depending on the manufacturing device has a limitation and enhancement of the recording density by multivalue storage has a limitation from the viewpoint of data integrity.
Therefore, recently, a stacked nonvolatile semiconductor memory device having memory cells stacked vertically by arranging gate electrodes of NAND cell units separately in a vertical direction on side surfaces of a column-shaped semiconductor layer is proposed (for example, Jpn. Pat. Appln. KOKAI Publication No. 2007-145661). In this device, first and second laminated bodies each configured by laminating a plurality of gate electrodes with insulating layers disposed therebetween are separately arranged on the substrate. A semiconductor layer that functions as active regions of the memory cells is filled between the laminated bodies. Further, a NAND cell unit is configured by serially connecting the memory cells formed on the first laminated body side and the memory cells formed on the second laminated body side. Then, an isolation insulating film used to isolate the right and left laminated bodies from each other is formed on the upper portion of the semiconductor layer.
However, since the column-shaped semiconductor layer is made to float in this type of nonvolatile semiconductor memory device, it is impossible to directly apply substrate potential to the semiconductor layer. For this reason, a variation occurs in voltages applied at the write and erase operation times. As a result, there occurs a problem that stable write and erase operations cannot be performed.